In order to increase the operating speed of a semiconductor device, various approaches have been proposed for decreasing a gate critical dimension (hereinafter referred to as “CD”) or optimizing ion implantation conditions. However, an improvement in the manufacturing equipment is required for optimizing the ion implantation conditions, and a great decrease of the gate CD affects a formation of silicide, thereby resulting in an interrupt of current flow.
For this reason, approaches for reducing the gate CD as well as decreasing a silicide resistance have recently been developed. Among such approaches, there has steadily been developed a process for forming a CD of an upper portion of the gate greater than that of a lower portion of the gate, thereby shortening a channel length of the gate to achieve high speed operation. However, most of the approaches proposed heretofore require a new process flow, thereby deteriorating the yield of the semiconductor device manufacturing process.
A conventional gate forming process is shown in FIGS. 1A and 1B. Referring to FIG. 1A, after cleaning a semiconductor substrate 1 (e.g., a silicon substrate), a gate insulation film 2 is formed on the semiconductor substrate 1. A gate polysilicon layer 3 for forming a gate electrode is deposited on the gate insulation film 2. A photoresist film is deposited on the gate polysilicon layer 3 and patterned, thereby forming a photoresist pattern 4 for use as an etching mask for forming a gate region.
As shown in FIG. 1B, by selectively dry etching the gate polysilicon layer 3 using the photoresist pattern 4 as a mask until the gate insulation film 2 is exposed, a gate electrode having a desired gate profile is formed. The photoresist pattern 4 is then removed. Sidewall polymers are then formed on the gate polysilicon layer 3 by sidewall polymerization resulting from etching gases supplied under certain process conditions. These sidewall polymers are then removed in a subsequent cleaning process.
An organic or inorganic antireflective coating (ARC) layer may be deposited on the gate polysilicon layer 3. In such a case, the ARC layer is first etched using the photoresist pattern 4 as a mask, (e.g., by an endpoint detection apparatus) before etching the gate polysilicon layer 3.
As shown in FIG. 1B, the gate profile formed by the conventional gate forming process shows that the CD of the lower portion of the gate is greater than or equal to that of the upper portion of the gate. As a result, the conventional gate forming process does not achieve the desired result of forming the CD of the upper portion greater than that of the lower portion.